|
Synopsys and Xilinx Deliver HDL Coding Guidelines for FPGAs
MOUNTAIN VIEW, Calif.----Oct. 26, 2000--Synopsys,
Inc.(Nasdaq:SNPS), the technology leader for complex IC design and
Xilinx, Inc. (Nasdaq:XLNX) the programmable logic leader, today
announced availability of the Xilinx® Coding Style 1.0 policy for
Synopsys' LEDA® family of hardware description language (HDL)
checkers.
The policy is a source file that is used to configure the LEDA
checkers. It contains the critical coding-style rules necessary to
ensure the design quality and workmanship needed to prevent design
flow bottlenecks in downstream tools, and optimize implementation area
and performance for Xilinx field programmable gate arrays (FPGAs). The
coding-style policy will also improve the team design process by
guiding engineering coding styles, such that they are more portable
and compliant with established design reuse practices. Finally, using
LEDA with the Xilinx Coding policy will help facilitate the migration
of application specific integrated circuit (ASIC) designs into FPGAs,
enabling faster time to market and more efficient design prototyping.
``Xilinx regards partnering with Synopsys on this initiative as a
critical step to help designers optimize their HDL coding styles when
targeting to Xilinx FPGAs,'' said Rich Sevcik, senior vice president of
IP, support and software at Xilinx. ``The LEDA technology will help
ASIC designers realize the time to market, density, and performance
benefits that Xilinx FPGAs now offer. The Xilinx coding style policy
for LEDA will guide ASIC designers on the subtle coding style
differences required for maximizing performance in Xilinx programmable
devices.''
The first version of Xilinx coding style policy for LEDA is
comprised of a special set of rules that includes Xilinx-provided,
FPGA-specific rules and FPGA-applicable rules, derived from the 300+
rules pre-packaged with Synopsys' LEDA programmable HDL checker. These
rules check for common mistakes and poor design practices related to
things like treatment of module inputs and outputs, resets,
inadvertent inferencing of latches, gating of clocks, etc. Xilinx
determined these rules to be critical for ensuring a smooth design
flow and maximizing performance from its newest architectures, such as
Virtex. Xilinx also customized the error-messages and documentation
for these rules to give designers additional guidance for optimizing
different tool-execution options and selecting microarchitecture-level
components.
``Since we released the Reuse Methodology Manual (RMM) and OpenMORE
guidelines back in 1998, Synopsys has led the EDA industry in
providing design reuse solutions for ASIC designers'' said John
Chilton, senior vice president and general manager of the IP and
Systems Group at Synopsys. ``Synopsys' FPGA Compiler II has long
offered support for the same DesignWare Foundation IP reuse library
that supports our ASIC tools. Today's announcement of unique FPGA
support with our LEDA technology is another step to facilitate FPGA
design with state-of-the-art EDA tools. Now that Xilinx is delivering
multimillion gate FPGAs, and offering high level approaches that
encourage team and IP-based designs, we see a great opportunity for
our design reuse expertise to assist teams working on FPGA projects.''
Availability
The Xilinx Coding Style 1.0 policy will be available December 2000
and can be downloaded free of charge from the Synopsys website to
current LEDA licensees.
About Xilinx
Xilinx is the leading innovator of complete programmable logic
solutions, including advanced integrated circuits, software design
tools, predefined system functions delivered as cores, and
unparalleled field engineering support. Founded in 1984 and
headquartered in San Jose, Calif., Xilinx invented the field
programmable gate array (FPGA) and fulfills more than half of the
world demand for these devices today. Xilinx solutions enable
customers to reduce significantly the time required to develop
products for the computer, peripheral, telecommunications, networking,
industrial control, instrumentation, high-reliability/military, and
consumer markets. For more information, visit the Xilinx web site at
www.xilinx.com.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View,
California, creates leading electronic design automation (EDA) tools
for the global electronics market. The company delivers advanced
design technologies and solutions to developers of complex integrated
circuits, electronic systems, and systems on a chip. Synopsys also
provides consulting and support services to simplify the overall IC
design process and accelerate time to market for its customers. Visit
Synopsys at http://www.synopsys.com.
Synopsys and LEDA are registered trademarks of Synopsys, Inc. FPGA
Compiler II is a trademark of Synopsys. All other trademarks or
registered trademarks mentioned in this release are the intellectual
property of their respective owners.
Contact:
Synopsys, Inc.
Meghan Le, 650/584-4832
meghan@synopsys.com
http://www.synopsys.com
or
KVO Public Relations
Judy Kahn, 650/919-2022
judy_kahn@kvo.com
or
Xilinx, Inc.
Craig Willert, 303/413-3237
craig.willert@xilinx.com
or
Ann Duft, 408/879-4726
publicrelations@xilinx.com
www.xilinx.com
|
